1. Field of the Invention
The present invention relates to a storage device that includes a digital read channel including digital filtering and digital automatic gain control devices, where the digital read channel is coupled to a variable speed storage device.
2. Background of the Invention
Magnetic tape is effectively used to store digital data. Data is written onto the magnetic tape by a write head. The write head converts a current signal containing the digital information into flux patterns which are written as field transitions onto the magnetic tape. The data is retrieved when the magnetic tape is passed by a read head. The read head passes over the magnetic medium and transduces the magnetic transitions into pulses in an analog read signal, which are then decoded by read channel circuitry to reproduce the digital sequence.
Decoding the pulses into a digital sequence can be performed by a simple pulse detector read channel or, as in more recent designs, by a partial response maximum likelihood (PRML) read channel. The PRML read channel scheme is preferred over the simpler pulse detection scheme because it decreases the necessary bandwidth, thereby allowing more data to be stored on the storage medium.
FIG. 1 is a block diagram of a PRML read channel 100 in accordance with the prior art. PRML read channel 100 receives an electronic signal from a read head 102. Read head 102 is included in a storage device, such as a disk drive or tape drive, and is used to retrieve data stored using the device. The storage device may be capable of operating at a variable speed. Thus, PRML read channel 100 must receive a variable rate clock 104 as an input.
PRML read channel 100 includes an analog portion 106 and a digital portion 108. An analog-to-digital converter (ADC) 110 receives an output from the analog portion 106, converts the output to a digital data sample signal, and provides the digital data sample signal to digital portion 108.
Analog portion 106 includes a preamplifier 112, an analog low pass filter 114 and an automatic gain control (AGC) circuit 116. Read head 102 outputs an analog read signal that is received by preamplifier 112 which amplifies the signal. Next, the amplified signal is input into analog low pass filter 114 which is used to filter noise content from the signal. The filtered signal is then input into AGC 116. The output of AGC 116 is provided as an input to ADC 110.
The output of ADC 110 is provided to a pulse shaping filter 118, typically implemented as a finite impulse response filter (FIR). The output of pulse shaping filter 118 is provided as an input to Viterbi detector 120.
Because the storage device is capable of operating at a variable speed, a programming line 122 is used to program analog low pass filter 114 and AGC 116 so that analog low pass filter 114 and AGC 116 will operate at each of the variable speeds. The analog filter and AGC are programmed so that they are optimized for the data transfer rate of the input signal. Thus, when the data transfer rate changes, the analog filter and AGC must be reprogrammed.
The variable speed operation of the device will change the frequencies over which filter 114 and AGC 116 must operate. As the range of clock rates increases, the range of programmability must increase. This increases the complexity, difficulty, and cost of analog low pass filter 114 and of AGC 116.
Another solution to providing filtering and gain control over a wide range of frequencies is to provide multiple filters and AGC circuits that must be switched in and out of the read channel. This will also increase the cost of the read channel.